Future Branches { beyond Speculative Execution

The performance and hardware complexity of superscalar architectures is hindered by conditional branch instructions. When conditional branches are encountered in a program, the instruction fetch unit must rapidly predict the branch predicate and begin speculatively fetching instructions with no loss of instruction throughput. Speculative execution increases hardware cost, since speculative instructions must be cleanly aborted if the branch is mis-predicted. Speculative execution also does not scale well for increasingly superscalar architectures, since mis-prediction probabilities and penalties grow as more branches are encountered. The future branch is an additional instruction that helps overcome the performance bottleneck of conditional branches. A future branch separates the speciication of a impending branch (and the conditional predicate) from the actual branch location. The future branch instruction includes a branch source address (the location of the impending conditional branch) in addition to the branch target. It begins computing the branch predicate immediately, prior to the branch source address being reached. If a future branch is scheduled early enough, the branch predicate can be resolved before the actual branch is encountered, thus avoiding speculative execution. This papers includes a detailed hardware design and cost evaluation for an implementation of the future branch for the Power PC 604. In addition, we describe the compiler algorithms and technology needed to generate future branch instructions. Further, we provide preliminary results, using a micro-architecture simulator, showing the performance gains obtained by using future branches.